1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of fabricating the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
The LCD device operated by the vertically induced electric field has a disadvantage in failing to achieve a wide viewing angle. To achieve a wide viewing angle, an IPS-LCD (in-plane switching mode LCD) device is suggested. The IPS-LCD device is operated by an in-plane electric field.
FIG. 1 is a view illustrating an IPS-LCD device according to the related art.
Referring to FIG. 1, the LCD device includes a lower substrate 10 referred to as an array substrate, an upper substrate 9 referred to as a color filter substrate, and a liquid crystal layer 11 between the two substrates 9 and 10. A common electrode 30 and a pixel electrode 17 are formed at the lower substrate 10 and induce an in-plane electric field L, and liquid crystal molecules of the liquid crystal layer 11 are operated by the in-plane electric field L.
FIGS. 2A and 2B are views illustrating the LCD device in off and on states, respectively, according to the related art.
Referring to FIGS. 2A and 2B, when the off state changes into the on state, an in-plane electric field L is induced between the common electrode 17 and the pixel electrode 30. While alignment of liquid crystal molecules 11 a over the common electrode 17 and the pixel electrode 30 do not change, alignment of liquid crystal molecules 11b between the common electrode 17 and the pixel electrode 30 change in accordance with the in-plane electric field L. Since the liquid crystal molecules are arranged in according with the in-plane electric field, wide viewing angle can be achieved.
FIG. 3 is a plan view illustrating an array substrate of an IPS-LCD device according to the related art, and FIG. 4 is a cross-sectional view taken along a line IV-IV of FIG. 3.
Referring to FIGS. 3 and 4, the array substrate includes a gate line 43 and a data line 60 crossing each other to define a pixel region P on a substrate 40. A common line 47 is spaced apart from the gate line 43.
A thin film transistor Tr is located in a switching region TrA at the crossing of the gate and data lines 43 and 60. The thin film transistor Tr includes a gate electrode 45, a semiconductor layer 51, and source and drain electrodes 53 and 55.
In the pixel region P, a plurality of pixel electrodes 70a and 70b and a plurality of common electrodes 49a and 49b are arranged alternately. The pixel electrodes 70a and 70b are connected to a connection pattern 69, and the connection pattern 69 is connected to the drain electrode 55. The common electrodes 49a and 49b are connected to the common line 47.
The array substrate is fabricated with five mask processes. For example, a first metal material is deposited on the substrate 40 and patterned in a first mask process to form a gate electrode 45, the gate line 43, the common electrodes 49a and 49b and the common line 47. A gate insulating layer 50 is formed on the substrate 40 having the gate electrode 45.
An intrinsic amorphous silicon (a-Si) layer and an impurity-doped amorphous silicon layer are sequentially formed on the gate insulating layer 50 and patterned in a second mask process to form a semiconductor layer 51. The semiconductor layer 51 includes an active layer 51a made of the intrinsic amorphous silicon and an ohmic contact layer 51b made of the impurity-doped amorphous silicon.
A second metal material is deposited on the substrate 40 having the semiconductor layer 51 and patterned in a third mask process to form the source and drain electrodes 53 and 55, and the data line 60. The ohmic contact layer 51b between the source and drain electrodes 53 and 55 is removed.
A passivation layer 65 is formed on the substrate 40 having the source and drain electrodes 53 and 55 and patterned in a fourth mask process to form a drain contact hole 67 exposing the drain electrode 55.
A transparent conductive material is deposited on the passivation layer 65 and patterned in a fifth mask process to form the pixel electrodes 49a and 49b. 
Through the above-described five mask processes, the array substrate is fabricated. However, since production time and cost increase as mask processes increase, it is needed to decrease the number of the mask processes.
FIG. 5 is a view illustrating an array substrate of an IPS-LCD device fabricated with four mask processes according to the related art.
Referring to FIG. 5, one mask process decreases compared to FIG. 4. That is, source and drain electrodes 84 and 86 and a data line 82 are formed in the same mask process of forming a semiconductor layer 79. Accordingly, a semiconductor pattern 80 having the same stacking structure as the semiconductor layer 79 is formed below the data line 82. The semiconductor layer 79 includes an active layer 79a made of intrinsic amorphous silicon and an ohmic contact layer 79b made of impurity-doped amorphous silicon, and in a similar manner, the semiconductor pattern 80 includes a first pattern 80a made of intrinsic amorphous silicon and a second pattern 80b made of impurity-doped amorphous silicon. Common electrodes 75a and 75b are formed in the same process of forming a gate electrode 77 in a switching region TrA, and the source and drain electrodes 84 and 86 contact the ohmic contact layer 79b. A connection pattern 90 contacts the drain electrode 86 through a drain contact hole 89 in a passivation layer 88, and pixel electrodes 91a and 91b are connected to the connection pattern 90. A gate insulating layer 78 is on the gate electrode 77.
Since the active layer 79a protrudes outside the ohmic contact layer 79b and the first pattern 80a protrudes outside the second pattern 80b, photo current of a thin film transistor Tr increases and off current thus increases. Further, since the first pattern 80a protrudes outside the second pattern 80b, wavy noise occurs when backlight is on or off, and aperture ratio decreases. Accordingly, display quality is degraded in the related art IPS-LCD device.